{"id":2217,"date":"2026-09-04T06:37:14","date_gmt":"2026-09-04T06:37:14","guid":{"rendered":"https:\/\/ewirexon.com\/sic-wafer-metrology-ttv-bow-warp-diamond-wire-saw\/"},"modified":"2026-09-11T08:25:39","modified_gmt":"2026-09-11T08:25:39","slug":"sic-wafer-metrology-ttv-bow-warp-diamond-wire-saw","status":"publish","type":"post","link":"https:\/\/ewirexon.com\/zh\/sic-wafer-metrology-ttv-bow-warp-diamond-wire-saw\/","title":{"rendered":"SiC Wafer Metrology After Diamond Wire Saw Cutting: TTV, Bow, Warp and Damage"},"content":{"rendered":"<!-- SEO Title: SiC Wafer Metrology After Diamond Wire Saw Cutting: TTV, Bow, Warp and Damage -->\n<!-- Meta Description: Build a SiC wafer metrology control plan after diamond wire saw cutting, covering TTV, flatness, bow, warp, edge chips and subsurface damage. -->\n<!-- Suggested URL Slug: sic-wafer-metrology-ttv-bow-warp-diamond-wire-saw -->\n\n<p>For a SiC wafer supplier, the cutting trial is not finished when the wire exits the boule. The useful result is a measurement record that explains whether the wafer can survive cleaning, grinding, polishing, epitaxy and device fabrication. Total thickness variation (TTV), flatness, bow, warp, roughness, edge chips and subsurface damage describe different failure modes. Treating them as one generic \u201csurface quality\u201d number hides risk.<\/p>\n\n<p>This matters as the industry scales 200 mm SiC and targets higher-voltage power conversion. Bosch says its Roseville site will produce and test SiC on 200 mm wafers from 2026, while Infineon has reported 200 mm product releases. At the system level, STMicroelectronics and Infineon are describing SiC in 800 VDC and high-density AI data-centre power paths. Bigger substrates and tighter reliability expectations make position-resolved metrology a manufacturing requirement.<\/p>\n\n<p>A diamond wire saw creates the first finished geometry, but it is only one stage in a chain. A stable measurement system lets process engineers separate incoming crystal defects from wire dynamics, fixture movement, handling damage and downstream removal. It also gives procurement teams a common basis for comparing an <em>ewirexon endless diamond wire saw<\/em>, a production web and alternative slicing methods.<\/p>\n\n<!-- IMAGE-1: Position-resolved SiC wafer metrology map after wire sawing; see image-prompts.md -->\n\n\n<figure class=\"wp-block-image size-large\"><img fetchpriority=\"high\" decoding=\"async\" width=\"1672\" height=\"941\" src=\"https:\/\/ewirexon.com\/wp-content\/uploads\/2026\/09\/sic-wafer-metrology-featured.png\" alt=\"An engineer measuring a sliced 200 mm SiC wafer on a non-contact wafer metrology system\" class=\"wp-image-2223\" title=\"\" srcset=\"https:\/\/ewirexon.com\/wp-content\/uploads\/2026\/09\/sic-wafer-metrology-featured.png 1672w, https:\/\/ewirexon.com\/wp-content\/uploads\/2026\/09\/sic-wafer-metrology-featured-300x169.png 300w, https:\/\/ewirexon.com\/wp-content\/uploads\/2026\/09\/sic-wafer-metrology-featured-1024x576.png 1024w, https:\/\/ewirexon.com\/wp-content\/uploads\/2026\/09\/sic-wafer-metrology-featured-768x432.png 768w, https:\/\/ewirexon.com\/wp-content\/uploads\/2026\/09\/sic-wafer-metrology-featured-1536x864.png 1536w, https:\/\/ewirexon.com\/wp-content\/uploads\/2026\/09\/sic-wafer-metrology-featured-18x10.png 18w, https:\/\/ewirexon.com\/wp-content\/uploads\/2026\/09\/sic-wafer-metrology-featured-600x338.png 600w\" sizes=\"(max-width: 1672px) 100vw, 1672px\" \/><figcaption class=\"wp-element-caption\">Post-saw metrology must connect wafer geometry to the cutting history, rather than reduce quality to one surface number.<\/figcaption><\/figure>\n\n<h2>Start with a clear measurement boundary<\/h2>\n\n<p>Write the condition of the wafer beside every result. A bow value measured on a warm wafer immediately after coolant exposure is not directly comparable with a value measured after cleaning and relaxation. Define the cleaning chemistry, drying method, temperature, waiting time, clamping state and reference plane. Use the same boundary for all suppliers and all wire conditions.<\/p>\n\n<p>Separate three checkpoints:<\/p>\n\n<ol>\n<li><strong>Incoming boule and blank:<\/strong> diameter, orientation, end crop, visible defects, runout and fixture datum.<\/li>\n<li><strong>As-sawn wafer:<\/strong> thickness, TTV, flatness, bow, warp, edge, roughness and damage before material is removed.<\/li>\n<li><strong>Post-finish wafer:<\/strong> the same geometry and surface metrics after the defined grinding, lapping or polishing step.<\/li>\n<\/ol>\n\n<p>The delta between checkpoints is often more valuable than an isolated number. If bow falls sharply after a thin grinding pass, residual stress or a damaged layer may be driving the as-sawn shape. If a position-dependent TTV pattern remains after finishing, the root cause may be wire path, guide alignment or fixture support rather than polishing.<\/p>\n\n\n<figure class=\"wp-block-image size-large\"><img decoding=\"async\" width=\"1672\" height=\"941\" src=\"https:\/\/ewirexon.com\/wp-content\/uploads\/2026\/09\/sic-wafer-ttv-bow-warp.png\" alt=\"Engineering cross sections distinguishing total thickness variation, bow and warp in a sliced wafer\" class=\"wp-image-2224\" title=\"\" srcset=\"https:\/\/ewirexon.com\/wp-content\/uploads\/2026\/09\/sic-wafer-ttv-bow-warp.png 1672w, https:\/\/ewirexon.com\/wp-content\/uploads\/2026\/09\/sic-wafer-ttv-bow-warp-300x169.png 300w, https:\/\/ewirexon.com\/wp-content\/uploads\/2026\/09\/sic-wafer-ttv-bow-warp-1024x576.png 1024w, https:\/\/ewirexon.com\/wp-content\/uploads\/2026\/09\/sic-wafer-ttv-bow-warp-768x432.png 768w, https:\/\/ewirexon.com\/wp-content\/uploads\/2026\/09\/sic-wafer-ttv-bow-warp-1536x864.png 1536w, https:\/\/ewirexon.com\/wp-content\/uploads\/2026\/09\/sic-wafer-ttv-bow-warp-18x10.png 18w, https:\/\/ewirexon.com\/wp-content\/uploads\/2026\/09\/sic-wafer-ttv-bow-warp-600x338.png 600w\" sizes=\"(max-width: 1672px) 100vw, 1672px\" \/><figcaption class=\"wp-element-caption\">TTV, bow and warp describe different geometric mechanisms and should not be used interchangeably in a supplier acceptance plan.<\/figcaption><\/figure>\n\n<h2>Use different metrics for different mechanisms<\/h2>\n\n<h3>Thickness and TTV<\/h3>\n\n<p>Thickness is a local dimension; TTV is the range between the thickest and thinnest measured points on the specified map. A single centre reading can miss a ring or edge pattern. Use a repeatable multi-point map that captures centre, intermediate radii and edge exclusion. For 200 mm material, record the coordinate system and keep the same clocking mark through the process.<\/p>\n\n<p>When a diamond wire saw produces a periodic thickness signature, compare its phase with guide spacing, wire oscillation and feed transitions. Do not average away a pattern that could challenge downstream chucking or epitaxy. A low lot average can coexist with a high maximum TTV at a specific web position.<\/p>\n\n<h3>Flatness, bow and warp<\/h3>\n\n<p>Flatness compares the wafer surface with a specified reference plane or best-fit plane. Bow describes the centre deviation of the median surface; warp describes the total range of that median surface. The definitions and reference conventions must be fixed before the trial. A clamped measurement can suppress the very deformation that a handler will see.<\/p>\n\n<p>Record whether front and back surfaces are both included and whether edge exclusion is applied. For thin wafers, thermal gradients, residual stress, adhesive thickness and handling can change the result within minutes. Repeat measurements after a controlled relaxation period and retain the time stamp.<\/p>\n\n<h3>Roughness and waviness<\/h3>\n\n<p>Roughness captures shorter-scale texture; waviness captures longer-scale form. Report the instrument, cutoff, scan direction, sampling length and filtering. A wire mark may look acceptable in a photograph while a directional scan reveals a process signature. Compare at least two orthogonal directions and sample more than one wafer position.<\/p>\n\n<h3>Edge chips and edge exclusion<\/h3>\n\n<p>Edge damage can reduce the usable diameter and can initiate fracture during cleaning, grinding or robot handling. Define maximum chip size, affected arc length, corner geometry and the edge-exclusion rule. Photograph representative defects with scale and record whether they originate at entry, breakthrough, fixture contact or manual handling.<\/p>\n\n<h2>Make subsurface damage visible<\/h2>\n\n<p>Surface appearance does not prove that the underlying SiC is sound. Brittle fracture can leave cracks and a damaged layer below the as-sawn surface. The 2026 review of ultra-fine diamond-wire slicing identifies saw marks, wafer warp, breakage and wire wear as connected industrial challenges. Earlier fixed-abrasive SiC work also explored scanning acoustic microscopy for nondestructive evaluation of subsurface damage.<\/p>\n\n<p>Choose a method that matches the decision. Cross-section polishing and microscopy can measure local crack depth but are destructive. Confocal or white-light interferometry describes surface morphology, not the full subsurface. Acoustic, optical or X-ray methods may provide screening, but each requires calibration on representative SiC. Report detection limits, sampling plan and uncertainty, not just a pass\/fail label.<\/p>\n\n<p>Link the measured damage layer to the finishing allowance. A supplier should explain how much material must be removed to reach the required surface and shape, and what evidence supports that allowance. If the allowance is a blanket number imported from silicon, the cost and yield model is incomplete.<\/p>\n\n<!-- IMAGE-2: Surface and subsurface damage measurement methods around a SiC wafer; see image-prompts.md -->\n\n\n<figure class=\"wp-block-image size-large\"><img decoding=\"async\" width=\"1672\" height=\"941\" src=\"https:\/\/ewirexon.com\/wp-content\/uploads\/2026\/09\/sic-wafer-metrology-sampling-map.png\" alt=\"Center, mid-radius and edge measurement locations linked to wafer position in a diamond multi-wire saw web\" class=\"wp-image-2225\" title=\"\" srcset=\"https:\/\/ewirexon.com\/wp-content\/uploads\/2026\/09\/sic-wafer-metrology-sampling-map.png 1672w, https:\/\/ewirexon.com\/wp-content\/uploads\/2026\/09\/sic-wafer-metrology-sampling-map-300x169.png 300w, https:\/\/ewirexon.com\/wp-content\/uploads\/2026\/09\/sic-wafer-metrology-sampling-map-1024x576.png 1024w, https:\/\/ewirexon.com\/wp-content\/uploads\/2026\/09\/sic-wafer-metrology-sampling-map-768x432.png 768w, https:\/\/ewirexon.com\/wp-content\/uploads\/2026\/09\/sic-wafer-metrology-sampling-map-1536x864.png 1536w, https:\/\/ewirexon.com\/wp-content\/uploads\/2026\/09\/sic-wafer-metrology-sampling-map-18x10.png 18w, https:\/\/ewirexon.com\/wp-content\/uploads\/2026\/09\/sic-wafer-metrology-sampling-map-600x338.png 600w\" sizes=\"(max-width: 1672px) 100vw, 1672px\" \/><figcaption class=\"wp-element-caption\">A spatial sampling map and preserved wire-web position make systematic process drift easier to identify.<\/figcaption><\/figure>\n\n<h2>Design a sampling map that finds process drift<\/h2>\n\n<p>A useful map is position-aware and time-aware. For an endless cut, record entry, middle and breakthrough. For a multi-wire web, retain each wafer\u2019s wire position and order. Add samples at the centre and edge of the boule, because maximum contact length and coolant evacuation can create radial differences.<\/p>\n\n<p>For each sample, retain:<\/p>\n\n<ul>\n<li>lot, boule, wafer number and clocking orientation;<\/li>\n<li>wire specification, age, speed, tension and feed profile;<\/li>\n<li>fixture, adhesive or support condition;<\/li>\n<li>coolant temperature, flow or pressure, filtration and solids condition;<\/li>\n<li>cut time, alarms, pauses, breaks and operator interventions;<\/li>\n<li>all geometry, surface, edge and damage results with instrument ID.<\/li>\n<\/ul>\n\n<p>Use control charts for the outputs that matter to release. Plot TTV, bow, warp, effective kerf, edge-chip rate and damage-layer depth separately. Annotate wire changes, guide maintenance, coolant-filter replacement and fixture resets. A sudden shift after a maintenance event is actionable evidence; a single blended average is not.<\/p>\n\n<h2>Connect metrology to diamond wire saw settings<\/h2>\n\n<p>Metrology becomes useful when the process team can test a cause. If TTV rises with contact length, evaluate feed compensation, wire bow and guide stiffness. If edge chips cluster at breakthrough, evaluate support, exit speed and adhesive release. If roughness and damage rise as the wire ages, inspect abrasive flattening, loading and coolant debris.<\/p>\n\n<p>\u4e00\u4e2a <a href=\"https:\/\/ewirexon.com\/zh\/diamond-wire-saw-landing-page\/\">Ewirexon endless diamond wire saw<\/a> is a practical platform for isolating these variables because one wire loop and one fixture can be studied over repeated cuts. Keep the cut condition stable while changing one factor. This makes the result easier to transfer to a production machine and prevents a multi-factor recipe from becoming impossible to debug.<\/p>\n\n<p>After the baseline is understood, a <a href=\"https:\/\/ewirexon.com\/zh\/diamond-multi-wire-saw-semiconductor-photovoltaic-wafer-cutting\/\">\u91d1\u521a\u77f3\u591a\u7ebf\u952f<\/a> can be assessed for throughput. The metrology plan must expand rather than shrink: map centre-to-edge web positions, inspect wafer-to-wafer order and look for common-cause patterns. Parallel output only creates value when the full set of wafers remains within the release boundary.<\/p>\n\n<h2>Compare suppliers without creating false precision<\/h2>\n\n<p>Require raw data and uncertainty. A supplier report should state the instrument model, calibration status, repeatability, reproducibility study or gauge capability evidence and the number of wafers measured. If two processes differ by less than the measurement uncertainty, describe them as equivalent within the trial rather than declaring a winner.<\/p>\n\n<p>Normalize the cost model to accepted wafers. The numerator should include crystal allocation, wire, coolant and filtration, machine and labour time, inspection, downtime and the removal allowance implied by damage. The denominator should be wafers that pass geometry, surface, edge and damage criteria. This prevents a fast process with hidden finishing or handling rejects from looking economical.<\/p>\n\n<p>Also record the cost of metrology itself. A high-throughput line may need automated thickness and shape scans, while a development lot may justify destructive cross-sections. The right system is the least expensive one that reliably detects the failure modes that can escape to epitaxy or device fabrication.<\/p>\n\n<!-- IMAGE-3: Position-aware SPC and supplier acceptance flow for SiC wafer metrology; see image-prompts.md -->\n\n<h2>Practical acceptance checklist<\/h2>\n\n<ul>\n<li>Are thickness and TTV measured with a fixed, position-resolved map?<\/li>\n<li>Are bow, warp and flatness defined with the same reference and edge exclusion?<\/li>\n<li>Are roughness and waviness reported with scan direction, cutoff and filtering?<\/li>\n<li>Are edge chips classified by size and arc length with traceable photographs?<\/li>\n<li>Is subsurface damage measured with a validated method and known detection limit?<\/li>\n<li>Does the sample plan include entry, maximum engagement and breakthrough?<\/li>\n<li>For multi-wire slicing, is each wafer tied to its web position and sequence?<\/li>\n<li>Are wire age, coolant solids, alarms and interventions included with the result?<\/li>\n<li>Is downstream removal allowance linked to measured damage rather than a default?<\/li>\n<li>Can the supplier provide raw files for lot-level SPC and cost analysis?<\/li>\n<\/ul>\n\n<h2>\u7ed3\u8bba<\/h2>\n\n<p>SiC wafer metrology after diamond wire saw cutting is a control system, not a cosmetic inspection. TTV, flatness, bow, warp, roughness, edge chips and subsurface damage answer different questions and must be measured under documented conditions. Position and wire-age data reveal the process mechanisms that a lot average conceals.<\/p>\n\n<p>Build the measurement plan around accepted wafer output and downstream risk. Use an endless diamond wire saw to isolate material and machine variables, then extend the same traceability to a diamond multi-wire saw when volume justifies parallel slicing. Ewirexon\u2019s <a href=\"https:\/\/ewirexon.com\/zh\/products\/sic-compound-semiconductor-processing\/\">SiC processing application<\/a> and <a href=\"https:\/\/ewirexon.com\/zh\/service-solutions\/process-parameter-consulting\/\">\u5de5\u827a\u53c2\u6570\u54a8\u8be2<\/a> pages can support trial planning, while the buyer\u2019s own calibrated measurement system should decide release.<\/p>\n\n<h2>\u5e38\u89c1\u95ee\u9898\u89e3\u7b54<\/h2>\n\n<h3>Is TTV enough to qualify a SiC wafer after slicing?<\/h3>\n<p>No. TTV describes thickness range on a defined map. It does not replace bow, warp, flatness, roughness, edge-chip or subsurface-damage measurements.<\/p>\n\n<h3>What is the difference between bow and warp?<\/h3>\n<p>Bow describes the centre deviation of the median surface from a reference plane, while warp describes the total range of that surface. The exact result depends on the agreed reference, clamping state and edge exclusion.<\/p>\n\n<h3>How can a supplier measure subsurface damage?<\/h3>\n<p>Options include destructive cross-section microscopy and calibrated acoustic, optical or X-ray screening. Select a method that detects the expected damage scale and report its uncertainty and sampling plan.<\/p>\n\n<h3>Why keep wafer position in a multi-wire web?<\/h3>\n<p>Wire tension, spacing, guide condition and coolant access can vary across the web. Position data exposes centre-to-edge patterns and common-cause failures that a lot average can hide.<\/p>\n\n<h3>When should metrology be automated?<\/h3>\n<p>Automate repeatable geometry and surface scans when volume or release risk justifies it. Keep calibrated reference samples and periodic destructive checks so the automated signal remains tied to actual damage and yield.<\/p>\n\n<h2>Technical references<\/h2>\n\n<ul>\n<li>Bosch, <a href=\"https:\/\/www.bosch-semiconductors.com\/roseville\/\" rel=\"noopener\" target=\"_blank\">Roseville 200 mm SiC wafer production<\/a>, accessed September 2026.<\/li>\n<li>Infineon Technologies, <a href=\"https:\/\/www.infineon.com\/technology\/ai\/we-power-ai\" rel=\"noopener\" target=\"_blank\">AI data-centre power path with SiC and GaN<\/a>, 2026.<\/li>\n<li>STMicroelectronics, <a href=\"https:\/\/newsroom.st.com\/media-center\/press-item.html\/f0022.html\" rel=\"noopener\" target=\"_blank\">Infrastructure of Cloud AI<\/a>, 26 June 2026.<\/li>\n<li>Ge et al., <a href=\"https:\/\/doi.org\/10.1016\/j.mssp.2025.110209\" rel=\"noopener\" target=\"_blank\">Progress and critical challenges in slicing of thin semiconductor wafers using ultra-fine diamond wire<\/a>, <em>Materials Science in Semiconductor Processing<\/em>, 2026.<\/li>\n<li>Li et al., <a href=\"https:\/\/pubs.rsc.org\/en\/content\/articlehtml\/2026\/ce\/d5ce00994d\" rel=\"noopener\" target=\"_blank\">Comparative study on substrate quality of laser slicing and wire saw slicing for SiC wafers<\/a>, <em>CrystEngComm<\/em>, 2026, DOI: 10.1039\/D5CE00994D.<\/li>\n<li><a href=\"https:\/\/doi.org\/10.1081\/AMP-120029960\" rel=\"noopener\" target=\"_blank\">Fixed abrasive diamond wire saw slicing of single-crystal silicon carbide wafers<\/a>, <em>Materials and Manufacturing Processes<\/em>.<\/li>\n<li>Sefene, Chen and Tsai, <a href=\"https:\/\/doi.org\/10.1016\/j.jmapro.2024.09.093\" rel=\"noopener\" target=\"_blank\">A comprehensive review of diamond wire sawing for single-crystal hard and brittle materials<\/a>, <em>Journal of Manufacturing Processes<\/em>, 2024.<\/li>\n<\/ul>\n\n<p><small><strong>Editorial note:<\/strong> This article was developed with AI-assisted research and English editing. Acceptance limits and metrology methods must be agreed with the device customer and validated on representative material. Three original AI illustrations are required before publication.<\/small><\/p>","protected":false},"excerpt":{"rendered":"<p>Build a SiC wafer metrology control plan after diamond wire saw cutting, covering TTV, flatness, bow, warp, edge chips and subsurface damage.<\/p>","protected":false},"author":1,"featured_media":2223,"comment_status":"open","ping_status":"open","sticky":false,"template":"","format":"standard","meta":{"_acf_changed":false,"footnotes":""},"categories":[28],"tags":[69,41,36,39,40,44,37,68],"class_list":["post-2217","post","type-post","status-publish","format-standard","has-post-thumbnail","hentry","category-product-technology-updates","tag-200-mm-sic","tag-diamond-multi-wire-saw","tag-diamond-wire-saw","tag-hard-brittle-material-cutting","tag-precision-diamond-wire-saw","tag-semiconductor-wafer-cutting","tag-sic-wafer-cutting","tag-sic-wafer-slicing"],"acf":[],"_links":{"self":[{"href":"https:\/\/ewirexon.com\/zh\/wp-json\/wp\/v2\/posts\/2217","targetHints":{"allow":["GET"]}}],"collection":[{"href":"https:\/\/ewirexon.com\/zh\/wp-json\/wp\/v2\/posts"}],"about":[{"href":"https:\/\/ewirexon.com\/zh\/wp-json\/wp\/v2\/types\/post"}],"author":[{"embeddable":true,"href":"https:\/\/ewirexon.com\/zh\/wp-json\/wp\/v2\/users\/1"}],"replies":[{"embeddable":true,"href":"https:\/\/ewirexon.com\/zh\/wp-json\/wp\/v2\/comments?post=2217"}],"version-history":[{"count":1,"href":"https:\/\/ewirexon.com\/zh\/wp-json\/wp\/v2\/posts\/2217\/revisions"}],"predecessor-version":[{"id":2226,"href":"https:\/\/ewirexon.com\/zh\/wp-json\/wp\/v2\/posts\/2217\/revisions\/2226"}],"wp:featuredmedia":[{"embeddable":true,"href":"https:\/\/ewirexon.com\/zh\/wp-json\/wp\/v2\/media\/2223"}],"wp:attachment":[{"href":"https:\/\/ewirexon.com\/zh\/wp-json\/wp\/v2\/media?parent=2217"}],"wp:term":[{"taxonomy":"category","embeddable":true,"href":"https:\/\/ewirexon.com\/zh\/wp-json\/wp\/v2\/categories?post=2217"},{"taxonomy":"post_tag","embeddable":true,"href":"https:\/\/ewirexon.com\/zh\/wp-json\/wp\/v2\/tags?post=2217"}],"curies":[{"name":"wp","href":"https:\/\/api.w.org\/{rel}","templated":true}]}}