AI data centers are changing the power path from the utility connection to the processor rack. The industry is moving from conventional low-voltage distribution toward higher-voltage direct-current architectures because large accelerator clusters concentrate more power in less floor space. Silicon carbide (SiC) is one of the wide-bandgap technologies being evaluated for the switches, circuit protection and conversion stages in that path. For wafer and equipment teams, the implication is practical: the substrate process must deliver repeatable geometry and damage control before a power device can benefit from a higher-voltage architecture.
The trend is no longer only a long-range concept. In June 2026, STMicroelectronics described SiC, GaN and 800 VDC architectures as part of the infrastructure required to scale AI factories from megawatts toward gigawatts. Infineon’s current AI power roadmap describes a transition from 48 V distribution toward three-phase HVDC and, eventually, DC microgrids with rack levels above 1 MW. The IEA’s 2026 electricity analysis also expects data-centre electricity use to grow rapidly through 2030 while global electricity demand accelerates.
Those system announcements do not define a wire-saw recipe. They do define a tougher manufacturing context. Power-device buyers will ask substrate suppliers for larger diameters, stable electrical properties, low defect density and traceable wafer geometry. A diamond wire saw remains a critical upstream operation because it determines how much crystal is recovered and how much surface and subsurface damage must be removed later.
Why an AI power trend matters to wafer slicing
A power architecture is only as efficient as its weakest conversion stage. The switch must withstand voltage, switch with acceptable losses and survive thermal cycling. The package must spread heat and maintain electrical isolation. The device fab must control epitaxy, junction termination and metallization. The substrate supplied to that fab sets the starting geometry, defect population and mechanical margin for every later step.
Higher-voltage systems increase the value of process consistency. A wafer that barely passes a thickness or bow limit may still create handling problems during epitaxy, lithography or thinning. A wafer with an unmeasured crack network can survive inspection but fail during grinding, polishing or thermal processing. This is why SiC wafer cutting should be managed as a capability study, not a single cutting-speed demonstration.
200 mm is a manufacturing decision, not only a diameter
Bosch states that its Roseville site will produce and test SiC semiconductors on 200 mm wafers from 2026. Infineon has reported product releases based on 200 mm SiC technology, and other substrate manufacturers are expanding 200 mm capacity. The commercial question is therefore how to achieve usable wafer output, not whether a machine can physically accept a 200 mm blank.
The larger section length increases the maximum number of simultaneously engaged diamond particles. Wire bow, flushing distance and fixture deflection become more sensitive to small changes in tension, guide condition and feed. A process window that is stable on a short coupon can become position-dependent on a full boule. For AI-power substrate supply, position-dependent variation is a yield risk because the downstream device line must process all wafer positions with the same recipe and release criteria.
Translate system requirements into slicing outputs
Do not start a supplier trial with an abstract request for “high quality.” Convert the power-device use case into measurable outputs:
- Geometry: target thickness, total thickness variation (TTV), flatness, bow and warp after a controlled clean and relaxation period.
- Surface: roughness, waviness, saw-mark distribution and edge condition before grinding or polishing.
- Subsurface: crack depth or damage-layer distribution measured with a validated destructive or imaging method.
- Material recovery: effective kerf at entry, centre and breakthrough, plus crop and end losses.
- Process stability: load or wire-bow trace, cut time, wire consumption, coolant condition and intervention history.
These metrics connect the sierra de hilo de diamante to the accepted-wafer denominator. For example, a thinner nominal wire may reduce physical kerf but increase lateral motion and subsurface damage. If the finishing allowance rises, the claimed reducción de la pérdida por corte is not a material-recovery improvement. The correct comparison is usable wafers per boule after the defined finishing and inspection boundary.
What 800 VDC changes in the process qualification plan
Control the starting material
Record polytype, conductivity type, crystal orientation, off-axis angle, diameter, usable length and incoming defect map. Keep material from one growth lot together for each comparison. Electrical targets downstream do not excuse poor incoming traceability: if a wafer fails after epitaxy, the team needs to know whether the cause began in growth, cropping, SiC wafer cutting or finishing.
Establish an endless-wire baseline
Un Ewirexon endless diamond wire saw gives a process engineer flexible access to the cut. Use it to compare wire construction, abrasive envelope, feed profile, tension and fixture support on representative material. Begin with a conservative condition that produces an explainable load trace. Map kerf, thickness and edge quality at several positions instead of optimizing one visually attractive wafer.
Use repeated cuts to separate setup variation from material response. Record the time required to load, align, cut, clean and inspect. If an operator must adjust coolant or feed every few minutes, record that intervention as part of the capability result. High-voltage power supply customers ultimately need repeatable wafers, not a recipe that works only with a specialist standing beside the machine.
Test contact-length compensation
Divide the cut into entry, maximum-engagement and breakthrough regions. Compare constant feed with a position-aware or load-aware profile. Watch whether the bow or force signal returns as engagement decreases. A persistent rise after the centre can indicate abrasive loading, inadequate debris evacuation, guide wear or fixture movement.
Recent work on rocking and variable-speed feeding of 4H-SiC supports a general principle: wire dynamics should be managed as geometry changes. It does not provide a universal parameter set. Your qualification should identify which control variable reduces peak load while preserving the required wafer geometry and damage margin.
Qualify wear, not just a fresh wire
Measure abrasive condition before and after a defined number of cuts. Track effective kerf, cut time, load, surface response and edge chips through break-in, stable life and the approach to replacement. A wire that never breaks can still consume crystal value if its kerf or damage drifts outside the finishing budget. Define replacement by loss of process margin, not by breakage alone.
Endless versus multi-wire production for AI-power substrates
An endless system is usually the better learning platform when geometry, orientation or material lots change frequently. It allows fixture and recipe experiments with less common-cause exposure. A sierra de hilo múltiple de diamante becomes attractive when demand is stable and the web can be used efficiently.
Parallel slicing creates a different risk profile. Tension, spacing, guide grooves and coolant distribution must be uniform across the web. One instability can affect many wafers, and centre-to-edge patterns may be hidden by a lot average. Transfer only the material-removal learning from the endless trial. Re-qualify web dynamics, wafer position effects, handling and cleaning on the multi-wire tool.
Connect slicing data to power-device economics
The IEA forecasts that data-centre electricity consumption will approach 945 TWh by 2030 in its base case, with accelerated servers contributing a large share of the increase. That does not mean every AI data centre will use SiC at every stage. It does mean that efficiency, power density and availability are becoming purchasing criteria across the power chain. Substrate suppliers should therefore present a transparent cost and capability story.
Use a lot-level equation:
Accepted substrate output = wafers sliced minus wafers rejected for geometry, edge, damage, contamination or handling.
Then calculate conversion cost per accepted wafer, including boule allocation, wire, coolant and filtration, labour, machine time, metrology, expected downtime and the finishing allowance caused by the as-sawn condition. Report averages and distributions. A low average cost with a long tail of damaged wafers is a poor foundation for a high-reliability power-device line.
Supplier data package for an 800 VDC program
Ask for the complete traceable package before comparing proposals:
- machine work envelope and demonstrated 200 mm contact length;
- wire construction, abrasive specification, guide condition and tension calibration;
- feed, speed, rocking or compensation profile and actual load or bow trace;
- coolant type, flow or pressure, filtration and solids-control practice;
- kerf distribution, thickness map, TTV, flatness, bow, warp and edge-chip results;
- surface roughness, waviness and subsurface-damage method;
- wire-age data, breaks, alarms, pauses and manual interventions;
- accepted-wafer yield and the downstream removal allowance used in the calculation.
Label each value as measured, calculated or assumed. The file should let a procurement team reproduce the comparison without relying on a marketing summary.
Conclusión
800 VDC AI data-centre architectures raise the value of efficient, reliable power conversion, but the upstream manufacturing response starts with substrate quality. A stable diamond wire saw process must control effective kerf, contact-length dynamics, coolant access, fixture support and subsurface damage on the full material section.
Use an endless diamond wire saw to learn the material response, then qualify a diamond multi-wire saw only after the single-cut process and metrology system are stable. Ewirexon’s SiC and compound-semiconductor processing application y asesoramiento sobre parámetros de proceso pages provide context for a trial. The final release decision should still be based on the buyer’s own boule lots, measurement system and accepted-wafer economics.
Preguntas frecuentes
Does an 800 VDC data-centre architecture require SiC wafers?
No. The architecture can combine silicon, SiC and GaN according to voltage, frequency, cost and reliability needs. The trend increases interest in wide-bandgap devices; it does not prescribe one substrate or one switch topology.
Why does AI power demand affect the upstream wire saw?
Higher power density and reliability increase the value of consistent device substrates. Slicing controls material recovery, geometry and part of the damage budget that later processes must remove.
Is 200 mm SiC automatically lower cost than 150 mm?
No. Larger diameter can improve fab productivity, but only if boule quality, slicing yield, finishing allowance and device yield support the transition. A larger wafer with unstable geometry can cost more.
When should a supplier move from endless to multi-wire slicing?
After representative endless-wire trials establish a stable material-removal and metrology baseline. The multi-wire web then needs separate qualification for tension uniformity, coolant distribution and wafer-position effects.
What is the most useful first acceptance metric?
Use accepted wafers per boule and per total cycle, supported by kerf, TTV, bow, warp, edge quality and subsurface-damage distributions. No single nominal wire or speed value proves capability.
Referencias técnicas
- Agencia Internacional de la Energía, Electricity Mid-Year Update 2026, 2026.
- Agencia Internacional de la Energía, Energy demand from AI, updated 2026.
- STMicroelectronics, STMicroelectronics and the infrastructure of Cloud AI, 26 June 2026.
- Infineon Technologies, We Power AI: data-centre power architecture, 2026.
- Bosch, Roseville 200 mm SiC wafer fab, accessed September 2026.
- Ge et al., Progress and critical challenges in slicing of thin semiconductor wafers using ultra-fine diamond wire, Materials Science in Semiconductor Processing, 2026.
- Sun et al., A rocking-floating-variable speed feeding mode for slicing single-crystal silicon carbide, International Journal of Mechanical Sciences, 2025.
Nota editorial: This article was developed with AI-assisted research and English editing. It describes engineering qualification logic, not guaranteed device performance or universal machine parameters. Three original AI illustrations are required before publication.
